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COMPUTER ENGINEERING (ENGLISH) PROGRAMME
COURSE DESCRIPTION
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Name of the Course Unit
| Code
| Year
| Semester
| In-Class Hours (T+P)
| Credit
| ECTS Credit
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OPERATING SYSTEMS |
COM208 |
2 |
4 |
3+0 |
3.0 |
5.0 |
No
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Key Learning Outcomes of the Course Unit
On successful completion of this course unit, students/learners will or will be able to:
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1 |
1- hardware support for operating systems: privileged mode execution, saving and restoring CPU state, traps and interrupts, timers, memory protection. Operating system techniques for protecting user and hardware resources. Overview of the key operating system abstractions and the use of system calls to manipulate them. | 2 |
2- Program execution, the process concept, process-related state, the process table, saving and restoring process state, the role of the scheduler | 3 |
3-Threads, process context switch vs thread switch, true concurrency vs pseudo concurrency, operating systems as concurrent programs, concurrency through multi-threading, concurrency through interrupt handling, concurrent access to shared memory, race conditions, mutual exclusion, synchronization primitives based on atomic instructions | 4 |
4- locks, spinlocks, mutex semaphores, counting semaphores, and their use in solutions to Producer Consumer synchronization | 5 |
5- Classic synchronization problems: Producer Consumer, Dining Philosophers, Readers and Writers, Sleeping Barber | 6 |
6- Monitors, condition variables, message passing, and their use in solutions to classic synchronization problems: Producer Consumer, Dining Philosophers, Readers and Writers, Sleeping Barber
calls | 7 |
7- Deadlock, livelock, deadlock detection, avoidance, and prevention | 8 |
8-Separation of policy from mechanism, scheduling mechanisms, preemptive vs non-preemptive scheduling, example scheduling policies, FIFO, round-robin, shortest job first, priority scheduling, Unix-style feedback scheduling, proportional share scheduling, lottery scheduling | 9 |
9- Memory addresses and binding, static and dynamic addresses translation, address translation using base and limit registers, memory management algorithms using linked lists and bitmaps, external and internal fragmentation, paged virtual memory. | 10 |
10- Physical address spaces, virtual address spaces, page table design, single-level and multi-level page tables, hardware support for dynamic address translation using a TLB, hardware and software managed TLB refill 11- Demand paging, swapping, placement and replacement algorithms, memory hierarchy revisited, overview of cache architecture, performance modeling for memory management systems 12- Devices, memory mapped devices, DMA, device drivers, interrupt handling, scheduled vs non-scheduled I/O processing, block vs character devices 13- Disks, sectors, tracks, blocks, disk head scheduling algorithms, the file abstraction, directories, links 14- File system architecture, file system data structures and system calls | |