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MECHATRONICS ENGINEERING (ENGLISH) PROGRAMME
COURSE DESCRIPTION
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Name of the Course Unit
| Code
| Year
| Semester
| In-Class Hours (T+P)
| Credit
| ECTS Credit
|
DIGITAL LOGIC DESIGN |
EEE206 |
2 |
4 |
3+0 |
3.0 |
5.0 |
Weekly Course Contents and Study Materials for Preliminary & Further Study |
Week |
Topics (Subjects) |
Preparatory & Further Activities |
1 |
1 Binary systems: Digital circuits, number systems, arithmetic operations, decimal codes, alphanumeric Codes. |
No file found
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2 |
2 Binary systems: Digital circuits, number systems, arithmetic operations, decimal codes, alphanumeric Codes |
No file found
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3 |
Boolean Algebra and Logic Gates:
Axiomatic definition of Boolean algebra, theorems and properties of Boolean algebra, canonical and standard forms of Boolean functions, other logic operations, digital logic gates, integrated circuits’ Law. |
No file found
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4 |
Boolean Algebra and Logic Gates:
Axiomatic definition of Boolean algebra, theorems and properties of Boolean algebra, canonical and standard forms of Boolean functions, other logic operations, digital logic gates, integrated circuits’ Law. |
No file found
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5 |
Simplification of Boolean functions:
The map method, prime implicants, product of sums simplification, two-level NAND and NOR implementations, other two-level implementations, don’t care conditions.
Midterm Examinations |
No file found
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6 |
Simplification of Boolean functions:
The map method, prime implicants, product of sums simplification, two-level NAND and NOR implementations, other two-level implementations, don’t care conditions. |
No file found
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7 |
Midterm Exam |
No file found
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8 |
Logic Implementations: multilevel NAND and NOR circuits, the tabulation method,Exclusive-OR function |
No file found
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9 |
Multilevel NAND and NOR circuits, the tabulation method, Exclusive-OR function |
No file found
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10 |
Combinational Logic: Analysis procedure, design procedure, code conversion, binaryadder-sub tractor, 4-bit parallel adder-subtractor, carry propagation, look-ahead carry generation, decimal adder. |
No file found
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11 |
Combinational Logic: Analysis procedure, design procedure, code conversion, binaryadder-sub tractor, 4-bit parallel adder-subtractor, carry propagation, look-ahead carry generation, decimal adder. |
No file found
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12 |
MSI components: magnitude comparator, decoders and encoders, priority encoders,Multiplexers, combinational logic implementation. |
No file found
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13 |
Synchronous sequential circuits: Flip-flops, triggering of flip-flops, analysis of Clocked sequential circuits, state reduction and assignment, flip-flop excitation tables, design procedure, design of counters |
No file found
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14 |
Synchronous sequential circuits: Flip-flops, triggering of flip-flops, analysis of Clocked sequential circuits, state reduction and assignment, flip-flop excitation tables, design procedure, design of counters |
No file found
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