KIUS
English


COMPUTER ENGINEERING (ENGLISH) PROGRAMME
COURSE DESCRIPTION
Name of the Course Unit Code Year Semester In-Class Hours (T+P) Credit ECTS Credit
COMPUTER ORGANIZATION COM202 2 4 3+0 3.0 5.0


General Information
Language of Instruction English
Level of the Course Unit Bachelor's Degree, TYYÇ: Level 6, EQF-LLL: Level 6, QF-EHEA: First Cycle
Type of the Course Compulsory
Mode of Delivery of the Course Unit Face-to-face
Work Placement(s) Requirement for the Course Unit No
Coordinator of the Course Unit
Instructor(s) of the Course Unit Dr. RUHSAN ÖNDER
Assistant(s) of the Course Unit

Prerequisites and/or co-requisities of the course unit
CATEGORY OF THE COURSE UNIT
Category of the Course Unit Degree of Contribution (%)
Fundamental Course in the field % 90
Course providing specialised skills to the main field % 10
Course providing supportive skills to the main field -
Course providing humanistic, communication and management skills -
Course providing transferable skills -

Objectives and Contents
Objectives of the Course Unit This course covers basics of modern computer organization and architectures. The emphasis is on understanding the interaction between computer hardware and software at various levels. The students will learn the concepts of computer technology, performance evaluation, instruction set design, computer arithmetic, data path and control unit design of processors and enhancing performance with pipelining.
Contents of the Course Unit -Interconnect engineering concepts related to instruction set architecture, register transfer, interconnects like buses, 3-state buffers and Muxes as well as control hardware to design various processors. -Learning to employ specialized knowledge of subsystems like data-path, memory and control unit components to design a RISC processing element. -Defining processor specification and instruction set architecture. -Solving various challenges of high performance RISC processor design in multiple stages
Contribution of the Course Intending to Provide the Professional Education On successful completion of this course, all students will have developed knowledge and understanding of: -Interconnect engineering concepts related to instruction set architecture, register transfer, interconnects like buses, 3-state buffers and Muxes as well as control hardware to design various processors. -Learn to employ specialized knowledge of subsystems like data-path, memory and control unit components to design a RISC processing element. -Define processor specification and instruction set architecture. -Solve various challenges of high performance RISC processor design in multiple stages

No
 Key Learning Outcomes of the Course Unit
On successful completion of this course unit, students/learners will or will be able to:
1 Interconnect engineering concepts related to instruction set architecture, register transfer, interconnects like buses, 3-state buffers and Muxes as well as control hardware to design various processors
2 Learn to employ specialized knowledge of subsystems like data-path, memory and control unit components to design a RISC processing element.
3 Define processor specification and instruction set architecture.
4 Solve various challenges of high performance RISC processor design in multiple stages

Learning Activities & Teaching Methods of the Course Unit
Learning Activities & Teaching Methods of the Course Unit

Weekly Course Contents and Study Materials for Preliminary & Further Study
Week Topics (Subjects) Preparatory & Further Activities
1 Computer Systems Technology: Computer Organization No file found
2 Computer Performance: Performance metrics & evaluation No file found
3 Instruction set Design: 1 Instruction representation.
2 Addressing modes.
3 Instructions for making decisions		 No file found
4 Instruction set Design: 1 Instruction representation.
2 Addressing modes.
3 Instructions for making decisions		 No file found
5 Arithmetic for computers: 1 Integer arithmetic operations
2 Logical operations
3 ALU Design and Implementation		 No file found
6 Arithmetic for computers: 1 Integer arithmetic operations
2 Logical operations
3 ALU Design and Implementation		 No file found
7 Data path: 1 Register transfer and Interconnection Structures
2 Data path Design		 No file found
8 Data path: 1 Register transfer and Interconnection Structures
2 Data path Design		 No file found
9 CPU Control Unit : Design No file found
10 CPU Control Unit : Implementation No file found
11 CPU Control Unit : Implementation No file found
12 Pipelining
1 Data Hazards		 No file found
13 Pipelining
2 Stalls and Forwarding		 No file found
14 Pipelining
3 Branch hazards		 No file found

SOURCE MATERIALS & RECOMMENDED READING
1-Patterson, David & Hennessy, John. “Computer Organization and Design: The Hardware/ Software Interface”. 4th ed., Morgan Kaufmann Publishers, Elsevier Inc., ISBN : 978-0-12-374-750-1

MATERIAL SHARING
Course Notes No file found
Presentations No file found
Homework No file found
Exam Questions & Solutions No file found
Useful Links No file found
Video and Visual Materials No file found
Other No file found
Announcements No file found

CONTRIBUTION OF THE COURSE UNIT TO THE PROGRAMME LEARNING OUTCOMES
KNOWLEDGE
Theoretical
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 Gaining knowledge on computer software, computer hardware, and computer networks with a strong background on mathematics X
2 Being able to design and implement both software and hardware of computer and computerized systems X
3 technical and practical knowledge X
Factual
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 Gained ability to be able to tackle with real-world cases X
SKILLS
Cognitive
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 Have insight into the latest technological developments in the contemporary societies X
2 using the technology for solving real-world problems X
3 being aware of real-world engineering tasks and problems X
Practical
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 practicing with real-world cases X
PERSONAL & OCCUPATIONAL COMPETENCES IN TERMS OF EACH OF THE FOLLOWING GROUPS
Autonomy & Responsibility
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 being able to use the technology to design and implement software and hardware of computer and computerized systems for solving real-world problems X
2 graduation projects on real-world cases X
3 summer practice at a workplace X
Learning to Learn
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 gain insight to the latest technological developments X
2 Being able to implement sustainable computerized systems both in software and hardware X
Communication & Social
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 being able to formulate mathematical models via communication of the problem word for designing and implementing solutions both in software and hardware X
Occupational and/or Vocational
No PROGRAMME LEARNING OUTCOMES LEVEL OF CONTRIBUTION*
0 1 2 3 4 5
1 Achieving a technically competent career X
2 Design and implement information and computing systems for the ever growing contemporary societies X
*Level of Contribution (0-5): Empty-Null (0), 1- Very Low, 2- Low, 3- Medium, 4- High, 5- Very High

No
 Key Learning Outcomes of the Course Unit
On successful completion of this course unit, students/learners will or will be able to: 		PROGRAMME LEARNING OUTCOMES
1 Interconnect engineering concepts related to instruction set architecture, register transfer, interconnects like buses, 3-state buffers and Muxes as well as control hardware to design various processors1 (5), 2 (4), 3 (5), 4 (5), 5 (5), 6 (5), 7 (5), 8 (5), 9 (5), 10 (2), 11 (2), 12 (5), 13 (5), 14 (5), 15 (5), 16 (5)
2 Learn to employ specialized knowledge of subsystems like data-path, memory and control unit components to design a RISC processing element.1 (5), 2 (4), 3 (5), 4 (5), 5 (5), 6 (5), 7 (5), 8 (5), 9 (5), 10 (2), 11 (2), 12 (5), 13 (5), 14 (5), 15 (5), 16 (5)
3 Define processor specification and instruction set architecture. 1 (5), 2 (4), 3 (5), 4 (5), 5 (5), 6 (5), 7 (5), 8 (5), 9 (5), 10 (2), 11 (2), 12 (5), 13 (5), 14 (5), 15 (5), 16 (5)
4 Solve various challenges of high performance RISC processor design in multiple stages1 (5), 2 (4), 3 (5), 4 (5), 5 (5), 6 (5), 7 (5), 8 (5), 9 (5), 10 (2), 11 (2), 12 (5), 13 (5), 14 (5), 15 (5), 16 (5)

Assessment
Assessment & Grading of In-Term Activities Number of
Activities		 Degree of Contribution (%)
Mid-Term Exam 0 -
Computer Based Presentation 0 -
Short Exam 0 -
Presentation of Report 0 -
Homework Assessment 0 -
Oral Exam 0 -
Presentation of Thesis 0 -
Presentation of Document 0 -
Expert Assessment 0 -
Board Exam 0 -
Practice Exam 0 -
Year-End Final Exam 0 -
Internship Exam 0 -
TOTAL 0 %100
Contribution of In-Term Assessments to Overall Grade 0 %50
Contribution of Final Exam to Overall Grade 1 %50
TOTAL 1 %100


WORKLOAD & ECTS CREDITS OF THE COURSE UNIT
Workload for Learning & Teaching Activities
Type of the Learning Activites Learning Activities
(# of week)		 Duration
(hours, h)		 Workload (h)
Lecture & In-Class Activities 14 3 42
Preliminary & Further Study 14 2 28
Land Surveying 0 0 0
Group Work 0 0 0
Laboratory 0 0 0
Reading 0 0 0
Assignment (Homework) 2 6 12
Project Work 0 0 0
Seminar 0 0 0
Internship 0 0 0
Technical Visit 0 0 0
Web Based Learning 0 0 0
Implementation/Application/Practice 0 0 0
Practice at a workplace 0 0 0
Occupational Activity 0 0 0
Social Activity 0 0 0
Thesis Work 0 0 0
Field Study 0 0 0
Report Writing 0 0 0
Total Workload for Learning & Teaching Activities - - 82
Workload for Assessment Activities
Type of the Assessment Activites # of Assessment Activities
 Duration
(hours, h)		 Workload (h)
Final Exam 1 3 3
Preparation for the Final Exam 1 40 40
Mid-Term Exam 0 0 0
Preparation for the Mid-Term Exam 0 0 0
Short Exam 0 0 0
Preparation for the Short Exam 0 0 0
Total Workload for Assessment Activities - - 43
Total Workload of the Course Unit - - 125
Workload (h) / 25.5 4.9
ECTS Credits allocated for the Course Unit 5.0

EBS : Kıbrıs İlim Üniversitesi Eğitim Öğretim Bilgi Sistemi Kıbrıs İlim Üniversitesi AKTS Bilgi Paketi AKTS Bilgi Paketi ECTS Information Package Avrupa Kredi Transfer Sistemi (AKTS/ECTS), Avrupa Yükseköğretim Alanı (Bologna Süreci) hedeflerini destekleyen iş yükü ve öğrenme çıktılarına dayalı öğrenci/öğrenme merkezli öğretme ve öğrenme yaklaşımı çerçevesinde yükseköğretimde uluslarası saydamlığı arttırmak ve öğrenci hareketliliği ile öğrencilerin yurtdışında gördükleri öğrenimleri kendi ülkelerinde tanınmasını kolaylaştırmak amacıyla Avrupa Komisyonu tarafından 1989 yılında Erasmus Programı (günümüzde Yaşam Boyu Öğrenme Programı) kapsamında geliştirilmiş ve Avrupa ülkeleri tarafından yaygın olarak kabul görmüş bir kredi sistemidir. AKTS, aynı zamanda, yükseköğretim kurumlarına, öğretim programları ve ders içeriklerinin iş yüküne bağlı olarak kolay anlaşılabilir bir yapıda tasarlanması, uygulanması, gözden geçirilmesi, iyileştirilmesi ve bu sayede yükseköğretim programlarının kalitesinin geliştirilmesine ve kalite güvencesine önemli katkı sağlayan bir sistematik yaklaşım sunmaktadır. ETIS : İstanbul Aydın University Education & Training System Cyprus Science University ECTS Information Package ECTS Information Package European Credit Transfer and Accumulation System (ECTS) which was introduced by the European Council in 1989, within the framework of Erasmus, now part of the Life Long Learning Programme, is a student-centered credit system based on the student workload required to achieve the objectives of a programme specified in terms of learning outcomes and competences to be acquired. The implementation of ECTS has, since its introduction, has been found wide acceptance in the higher education systems across the European Countries and become a credit system and an indispensable tool supporting major aims of the Bologna Process and, thus, of European Higher Education Area as it makes teaching and learning in higher education more transparent across Europe and facilitates the recognition of all studies. The system allows for the transfer of learning experiences between different institutions, greater student mobility and more flexible routes to gain degrees. It also offers a systematic approach to curriculum design as well as quality assessment and improvement and, thus, quality assurance.